1. Field of the Invention
The present invention relates to electrostatic discharge ESD conduction devices for mixed power integrated circuits, particularly for providing noise isolation and ESD conduction between power buses having similar voltage levels in such mixed power integrated circuits.
2. Description of Related Art
Mixed power integrated circuits are being developed for a wide variety of applications. Such integrated circuits include circuits that operate based on different power supply arrangements. Mixed power integrated circuits can be characterized as including multiple power domains, where a power domain comprises circuits coupled to a power supply bus network that is separated from the power supply bus networks of other domains. For example, integrated circuits having digital circuits and analog circuits often provide a digital domain having a digital power supply bus network with both digital power and digital ground buses coupled to the digital circuits, and an analog domain having an analog power supply bus network with both analog power and analog ground buses coupled to the analog circuits. Some mixed power integrated circuits include multiple digital domains, with or without an analog domain. Some mixed power integrated circuits include multiple analog domains, with or without a digital domain. The power supply bus networks for the independent domains are separated in order to avoid coupling of noise between the circuits in the separate domains, and to allow the magnitude of the power supply voltages to be varied amongst the circuits in the separate domains on the device.
FIG. 1 illustrates a prior art arrangement for a mixed power integrated circuit. In the arrangement shown in FIG. 1, an I/O pin 10 is coupled to an internal circuit 111 on the integrated circuit. Basic ESD protection for the pin 10 is provided with respect to a global power supply VCCO bus 12 by a diode 13, and with respect to a global ground VSSO bus 14 by a diode 15. The internal circuit 11 is coupled to local power supply VCCI bus 16 and to local ground VSSI bus 17. An ESD clamp 18 is coupled between the local power supply VCCI bus 16 and the local ground VSSI bus 17 which operates according to well-known principles to prevent the voltage difference between the two from exceeding a safe level during an ESD event. A diode 19, having its cathode coupled to the local power supply VCCI bus 16 and its anode to the local ground VSSI bus 17 provides protection from an ESD event which would cause the local ground VSSI bus 17 to exceed the voltage on the local power supply VCCI bus 16.
In the arrangement illustrated in FIG. 1, the global power supply VCCO bus 12 and the local power supply VCCI bus 16 are coupled together by an ESD conduction cell 21. Likewise the global ground VSSO bus 14 and the local ground VSSI bus 17 are coupled together by an ESD conduction cell 20. The ESD conduction cells are typically arranged as shown in FIG. 2 or FIG. 3 as pairs of counter parallel diode strings, which isolate the buses in the separate domains during normal operation, but allow conduction during an ESD event. Although this arrangement works suitably in some environments, a weakness is induced because of the finite resistance of the ESD conduction cells, symbolized by the resistor symbol within the block of ESD cell 20. Thus, the global ground VSSO bus 14 and the local ground VSSI bus 17 are separated such that this finite resistance affects the ESD conduction path. If an ESD pulse is applied to the pin 10, the ESD current is supposed to proceed along Path 1 through the ESD conduction cell 20 and the ESD power clamp 18, thereby protecting the internal circuit 11. However if the resistance in the ESD conduction cell 20 is too high, and the voltage difference caused is high enough to overstress and damage devices in the internal circuit 11, then the ESD current may discharge along Path 2, further damaging the device.
Thus, as can be seen, mixed power integrated circuits may lack sufficient ESD discharge paths in some configurations. It is desirable therefore to provide an ESD conduction device providing the needed noise isolation, and low resistance discharge during an ESD event, and to provide mixed power integrated circuits utilizing such devices.